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19-0381; Rev 2; 9/01
Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface
_______________General Description
The MAX197 multi-range, 12-bit data-acquisition system (DAS) requires only a single +5V supply for operation, yet accepts signals at its analog inputs that may span both above the power-supply rail and below ground. This system provides 8 analog input channels that are independently software programmable for a variety of ranges: 10V, 5V, 0V to +10V, or 0V to +5V. This increases effective dynamic range to 14 bits, and provides the user flexibility to interface 4mA-to-20mA, 12V, and 15V powered sensors to a single +5V system. In addition, the converter is overvoltage tolerant to 16.5V; a fault condition on any channel does not affect the conversion result of the selected channel. Other features include a 5MHz bandwidth track/hold, a 100ksps throughput rate, software-selectable internal or external clock and acquisition, 8+4 parallel interface, and an internal 4.096V or an external reference. A hardware SHDN pin and two programmable powerdown modes (STBYPD, FULLPD) are provided for lowcurrent shutdown between conversions. In STBYPD mode, the reference buffer remains active, eliminating start-up delays. The MAX197 employs a standard microprocessor (P) interface. A three-state data I/O port is configured to operate with 8-bit data buses, and data-access and bus-release timing specifications are compatible with most popular Ps. All logic inputs and outputs are TTL/CMOS compatible. The MAX197 is available in 28-pin DIP, wide SO, SSOP, and ceramic SB packages. For a different combination of ranges (4V, 2V, 0V to 4V, 0V to 2V), refer to the MAX199 data sheet. For 12-bit bus interface, refer to the MAX196 and MAX198 data sheets.
KIT ATION LE EVALU VAILAB LA MANUA
____________________________Features
o 12-Bit Resolution, 1/2LSB Linearity o Single +5V Operation o Software-Selectable Input Ranges: 10V, 5V, 0V to 10V, 0V to 5V o Fault-Protected Input Multiplexer (16.5V) o 8 Analog Input Channels o 6s Conversion Time, 100ksps Sampling Rate o Internal or External Acquisition Control o Internal 4.096V or External Reference o Two Power-Down Modes o Internal or External Clock
MAX197
______________Ordering Information
PART MAX197ACNI TEMP RANGE 0C to +70C PIN-PACKAGE 28 Narrow Plastic DIP
MAX197BCNI 0C to +70C 28 Narrow Plastic DIP MAX197ACWI 0C to +70C 28 Wide SO MAX197BCWI 0C to +70C 28 Wide SO MAX197ACAI 0C to +70C 28 SSOP MAX197BCAI 0C to +70C 28 SSOP MAX197BC/D 0C to +70C Dice* Ordering Information continued at end of data sheet. *Dice are specified at TA = +25C, DC parameters only.
__________________Pin Configuration
TOP VIEW
CLK 1 CS 2 WR 3 RD 4 28 DGND 27 VDD 26 REF 25 REFADJ
________________________Applications
Industrial-Control Systems Robotics Data-Acquisition Systems Automatic Testing Systems Medical Instruments Telecommunications
HBEN 5 SHDN 6 D7 7 D6 8 D5 9 D4 10 D3/D11 11 D2/D10 12 D1/D9 13 D0/D8 14
MAX197
24 INT 23 CH7 22 CH6 21 CH5 20 CH4 19 CH3 18 CH2 17 CH1 16 CH0 15 AGND
Functional Diagram appears at end of data sheet.
DIP/SO/SSOP/Ceramic SB 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface MAX197
ABSOLUTE MAXIMUM RATINGS
VDD to AGND............................................................-0.3V to +7V AGND to DGND.....................................................-0.3V to +0.3V REF to AGND..............................................-0.3V to (VDD + 0.3V) REFADJ to AGND.......................................-0.3V to (VDD + 0.3V) Digital Inputs to DGND...............................-0.3V to (VDD + 0.3V) Digital Outputs to DGND ............................-0.3V to (VDD + 0.3V) CH0-CH7 to AGND ..........................................................16.5V Continuous Power Dissipation (TA = +70C) Narrow Plastic DIP (derate 14.29mW/C above +70C)....1143mW Wide SO (derate 12.50mW/C above +70C)..............1000mW SSOP (derate 9.52mW/C above +70C) ......................762mW Narrow Ceramic SB (derate 20.00mW/C above +70C)..1600mW Operating Temperature Ranges MAX197_C_ _ .......................................................0C to +70C MAX197_E_ _.....................................................-40C to +85C MAX197_M_ _ ..................................................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER ACCURACY (Note 1) Resolution Integral Nonlinearity Differential Nonlinearity INL DNL Unipolar Offset Error Bipolar Channel-to-Channel Offset Error Matching Unipolar Bipolar Unipolar Gain Error (Note 2) Bipolar Gain Temperature Coefficient (Note 2) Unipolar Bipolar MAX197A MAX197B Up to the 5th harmonic 80 50kHz, VIN = 5V (Note 3) External CLK mode/external acquisition control External CLK mode/external acquisition control Internal CLK mode/internal acquisition control (Note 4) -86 15 <50 10 70 69 -85 -78 MAX197A MAX197B MAX197A MAX197B 3 5 MAX197A MAX197B MAX197A MAX197B 0.1 0.5 7 10 7 10 ppm/C LSB MAX197A MAX197B 12 1/2 1 1 3 5 5 10 LSB LSB Bits LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 10Vp-p, fSAMPLE = 100ksps) Signal-to-Noise + Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Aperture Delay SINAD THD SFDR dB dB dB dB ns ps ns
Aperture Jitter
2
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Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER ANALOG INPUT Track/Hold Acquisition Time fCLK = 2.0MHz 10V range Small-Signal Bandwidth -3dB rolloff 5V range 0V to 10V range 0V to 5V range Unipolar Input Voltage Range (See Table 1) Bipolar Unipolar Input Current Bipolar Input Dynamic Resistance Input Capacitance INTERNAL REFERENCE REF Output Voltage REF Output Tempco Output Short-Circuit Current Load Regulation Capacitive Bypass at REF REFADJ Output Voltage REFADJ Adjustment Range Buffer Voltage Gain REFERENCE INPUT (Buffer disabled, reference input applied to REF pin) Input Voltage Range Input Current Normal or STANDBY power-down mode VREF = 4.18V FULL power-down mode Normal or STANDBY power-down mode FULL power-down mode 2.4 4.18 400 A 1 10 5 VDD - 50mV k M V V With recommended circuit (Figure 1) 0mA to 0.5mA output current (Note 6) 4.7 2.465 2.500 1.5 1.6384 2.535 VREF TC VREF TA = +25C 4.076 4.096 40 30 7.5 4.116 V ppm/C mA mV F V % V/V Unipolar Bipolar (Note 5) 0V to 10V range 0V to 5V range -10V to 10V range -5V to 5V range -1200 -600 21 16 40 0 0 -10 -5 5 2.5 2.5 1.25 10 5 10 5 720 360 720 360 k pF A V MHz 3 s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX197
Input Resistance REFADJ Threshold for Buffer Disable
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Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface MAX197
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER POWER REQUIREMENTS Supply Voltage VDD Normal mode, bipolar ranges Supply Current IDD Normal mode, unipolar ranges Standby power-down (STBYPD) Full power-down mode (FULLPD) (Note 7) Power-Supply Rejection Ratio (Note 8) TIMING Internal Clock Frequency External Clock Frequency Range fCLK fCLK tACQI Acquisition Time tACQE Conversion Time Throughput Rate Bandgap Reference Start-Up Time Reference Buffer Settling tCONV Internal acquisition External CLK Internal CLK CCLK = 100pF 1.25 0.1 3.0 3.0 3.0 5 6.0 6.0 62 200 CREF = 4.7F CREF = 33F 2.4 0.8 VIN = 0V or VDD (Note 5) VDD = 4.75V, ISINK = 1.6mA VDD = 4.75V, ISOURCE = 1mA (Note 5) VDD - 1 15 10 15 0.4 8 60 7.7 10.0 100 s ksps s ms 5.0 s 1.56 2.00 2.0 MHz MHz PSRR External reference = 4.096V Internal reference 1/2 6 700 4.75 5.25 18 10 850 120 1/2 V mA A LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
External acquisition (Note 9) After FULLPD or STBYPD External CLK Internal CLK, CCLK = 100pF External CLK Internal CLK, CCLK = 100pF Power-up (Note 10) To 0.1mV REF bypass capacitor fully discharged
DIGITAL INPUTS (D7-D0, CLK, RD, WR, CS, HBEN, SHDN) (Note 11) Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance Output Low Voltage Output High Voltage Three-State Output Capacitance VINH VINL IIN CIN VOL VOH COUT V V A pF V V pF
DIGITAL OUTPUTS (D7-D4, D3/D11, D2/D10, D1/D9, D0/D8, INT)
4
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Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface
TIMING CHARACTERISTICS
(VDD = 5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER CS Pulse Width WR Pulse Width CS to WR Setup Time CS to WR Hold Time CS to RD Setup Time CS to RD Hold Time CLK to WR Setup Time CLK to WR Hold Time Data Valid to WR Setup Data Valid to WR Hold RD Low to Output Data Valid HBEN High or HBEN Low to Output Valid RD High to Output Disable RD Low to INT High Delay Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: SYMBOL tCS tWR tCSWS tCSWH tCSRS tCSRH tCWS tCWH tDS tDH tDO tDO1 tTR tINT1 Figure 2, CL = 100pF (Note 12) Figure 2, CL = 100pF (Note 12) (Note 13) 60 0 120 120 70 120 CONDITIONS MIN 80 80 0 0 0 0 100 50 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX197
Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply Rejection test. Tested for the 10V input range. External reference: VREF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB. Ground "on" channel; sine wave applied to all "off" channels. Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz. Guaranteed by design. Not tested. Use static loads only. Tested using internal reference. PSRR measured at full-scale. External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD = high control byte. Not subject to production testing. Provided for design guidance only. All input control signals specified with tR = tF = 5ns from a voltage level of 0.8V to 2.4V. tDO and tDO1 are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V. tTR is defined as the time required for the data lines to change by 0.5V.
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Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface MAX197
__________________________________________Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL CODE
MAX197-1
FFT PLOT
MAX197-2
EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY
FSAMPLE = 100kHz EFFECTIVE NUMBER OF BITS 11.5
MAX197-3
0.250 INTEGRAL NONLINEARITY (LSB) 0.200 0.150
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 fTONE = 10kHz fSAMPLE = 100kHz
12.0
0.100 0.050 0.000 -0.050 -0.100 -0.150 0 1000 2000 3000 4000 DIGITAL CODE
11.0
10.5
10.0 0 25 FREQUENCY (kHz) 50 1 10 INPUT FREQUENCY (kHz) 100
REFERENCE OUTPUT VOLTAGE (VREF) vs. TEMPERATURE
MAX197-4
POWER-SUPPLY REJECTION RATIO vs. TEMPERATURE
VDD = 5V 0.25V 0.2 PSRR (LSB) 0 100Hz -0.2 120Hz
MAX197-5 MAX197-7
4.100
0.4
4.095 VREF (V)
4.090 AV = 1.6384 +2.5V INTERNAL REFERENCE REFADJ
4.085
REF
-0.4
4.080 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
-0.6 -70 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING vs. TEMPERATURE
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING (LSB)
MAX197-6
CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING vs. TEMPERATURE
0.33 CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING (LSB) 0.32 0.31 0.30 0.29 0.28 0.27 -70 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
0.20
0.18
0.16
0.14
0.12
0.10 -70 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
6
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Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7-10 11 12 13 14 15 16-23 24 25 NAME CLK CS WR RD HBEN SHDN D7-D4 D3/D11 D2/D10 D1/D9 D0/D8 AGND CH0-CH7 INT REFADJ FUNCTION Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode, place a capacitor from this pin to ground to set the internal clock frequency; fCLK = 1.56MHz typical with CCLK = 100pF. Chip Select, active low. When CS is low, in the internal acquisition mode, a rising edge on WR latches in configuration data and starts an acquisition plus a conversion cycle. When CS is low, in the external acquisition mode, the first rising edge on WR starts an acquisition and a second rising edge on WR ends acquisition and starts a conversion cycle. If CS is low, a falling edge on RD will enable a read operation on the data bus. Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus; when low, the 8 LSBs are available on the bus. Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low. Three-State Digital I/O Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high). Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high). Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high). Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB. Analog Ground Analog Input Channels INT goes low when conversion is complete and output data is ready. Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01F capacitor to AGND. Connect to VDD when using an external reference at the REF pin. Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD. +5V Supply. Bypass with 0.1F capacitor to AGND. Digital Ground
MAX197
26 27 28
REF VDD DGND
+5V
+5V 510k 100k 0.01F 24k a. HIGH-Z TO VOH AND VOL TO VOH REFADJ
3k
MAX197
DOUT DOUT 3k CLOAD CLOAD
b. HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Reference-Adjust Circuit
Figure 2. Load Circuits for Enable Time 7
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Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface MAX197
_______________Detailed Description
Converter Operation
The MAX197, a multi-range, fault-tolerant ADC, uses successive approximation and internal input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. The parallel-output format provides easy interface to microprocessors (Ps). Figure 3 shows the MAX197 in its simplest operational configuration. mode with an external clock frequency of 2MHz, a 100ksps throughput rate can be achieved. It is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended (MAX274/MAX275 continuous-time filters).
Input Range and Protection
Figure 4 shows the equivalent input circuit. With VREF = 4.096V, the MAX197 can be programmed for input ranges of 10V, 5V, 0V to 10V, or 0V to 5V by setting the appropriate control bits (D3, D4) in the control byte (see Tables 2 and 3). The full-scale input voltage depends on the voltage at REF (Table 1). When an external reference is applied at REFADJ, the voltage at REF is given by VREF = 1.6384 x VREFADJ (2.4V < VREF < 4.18V).
Analog-Input Track/Hold
In the internal acquisition control mode (control bit D5 set to 0), the T/H enters its tracking mode on WR's rising edge, and enters its hold mode when the internally timed (6 clock cycles) acquisition interval ends. A low impedance input source, which settles in less than 1.5s, is required to maintain conversion accuracy at the maximum conversion rate. In the external acquisition control mode (D5 = 1), the T/H enters its tracking mode on the first WR rising edge and enters its hold mode when it detects the second WR rising edge with D5 = 0. See the External Acquisition section.
Table 1. Full Scale and Zero Scale
RANGE (V) ZERO SCALE (V) -FULL SCALE +FULL SCALE 0 to 5 0 to 10 5 10 0 0 -- -- -- -- VREF x 1.2207 VREF x 2.4414
Input Bandwidth
The ADC's input tracking circuitry has a 5MHz smallsignal bandwidth. When using the internal acquisition
-VREF x 1.2207 VREF x 1.2207 -VREF x 2.4414 VREF x 2.4414
1 100pF 2 P CONTROL INPUTS 3 4 5 6 7 8 9 10
CLK
DGND
28 S1 +5V +4.096V 0.1F 4.7F 12.5k CH_ S2 5.12k
BIPOLAR
VOLTAGE REFERENCE
MAX197 VDD 27
CS WR RD HBEN SHDN D7 D6 D5 INT CH7 CH6 CH5 CH4 CH3 CH2 REF REFADJ 26 25 24 23 22 21 20 19 18
UNIPOLAR
OUTPUT STATUS
OFF CHOLD ON T/H OUT
D4 11 D3/D11 12 D2/D10 13 D1/D9 14 D0/D8
ANALOG INPUTS
8.67k S3 HOLD TRACK TRACK S4 HOLD
CH1 17 16 CH0 AGND 15
S1 = BIPOLAR/UNIPOLAR SWITCH S2 = INPUT MUX SWITCH S3, S4 = T/H SWITCH
P DATA BUS
Figure 3. Operational Diagram 8
Figure 4. Equivalent Input Circuit
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Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface
The input channels are overvoltage protected to 16.5V. This protection is active even if the device is in power-down mode. Even with VDD = 0V, the input resistive network provides current-limiting that adequately protects the device. Input Format The control byte is latched into the device, on pins D7-D0, during a write cycle. Table 2 shows the controlbyte format. Output Data Format The output data format is binary in unipolar mode and twos-complement binary in bipolar mode. When reading the output data, CS, and RD must be low. When HBEN is low, the lower eight bits are read. When HBEN is high, the upper four MSBs are available and the output data bits D4-D7 are either set low (in unipolar mode) or set to the value of the MSB (in bipolar mode) (Table 6).
MAX197
Digital Interface
Input data (control byte) and output data are multiplexed on a three-state parallel interface. This parallel I/O can easily be interfaced with a P. CS, WR, and RD control the write and read operations. CS is the standard chipselect signal, which enables a P to address the MAX197 as an I/O port. When high, it disables the WR and RD inputs and forces the interface into a high-Z state.
Table 2. Control-Byte Format
D7 (MSB) PD1 BIT 7, 6 5 4 3 2, 1, 0 D6 PD0 NAME PD1, PD0 ACQMOD RNG BIP A2, A1, A0 D5 ACQMOD D4 RNG D3 BIP D2 A2 D1 A1 D0 (LSB) A0
DESCRIPTION These two bits select the clock and power-down modes (Table 4). 0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition Selects the full-scale voltage magnitude at the input (Table 3). Selects unipolar or bipolar conversion mode (Table 3). These are address bits for the input mux to select the "on" channel (Table 5).
Table 3. Range and Polarity Selection
BIP 0 0 1 1 RNG 0 1 0 1 INPUT RANGE (V) 0 to 5 0 to 10 5 10
Table 4. Clock and Power-Down Selection
PD1 PD0 0 0 1 1 0 1 0 1 DEVICE MODE Normal Operation / External Clock Mode Normal Operation / Internal Clock Mode Standby Power-Down (STBYPD); clock mode is unaffected Full Power-Down (FULLPD); clock mode is unaffected
Table 5. Channel Selection
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
-- -- -- -- -- -- -- --
9
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Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface MAX197
Table 6. Data-Bus Output
PIN D0 D1 D2 D3 D4 D5 D6 D7 HBEN = LOW B0 (LSB) B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 (MSB) B11 (BIP = 1) / 0 (BIP = 0) B11 (BIP = 1) / 0 (BIP = 0) B11 (BIP = 1) / 0 (BIP = 0) B11 (BIP = 1) / 0 (BIP = 0) HBEN = HIGH
Writing a new control byte during conversion cycle will abort conversion and start a new acquisition interval. Internal Acquisition Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose duration is internally timed. Conversion starts when this six-clock-cycle acquisition interval (3s with fCLK = 2MHz) ends. See Figure 5. External Acquisition Use the external acquisition timing mode for precise control of the sampling aperture and/or independent control of acquisition and conversion times. The user controls acquisition and start-of-conversion with two separate write pulses. The first pulse, written with ACQMOD = 1, starts an acquisition interval of indeterminate length. The second write pulse, written with ACQMOD = 0, terminates acquisition and starts conversion on WR's rising edge (Figure 6). However, if the second control byte contains ACQMOD = 1, an indefinite acquisition interval is restarted. The address bits for the input mux must have the same values on the first and second write pulses. Powerdown mode bits (PD0, PD1) can assume new values on the second write pulse (see Power-Down Mode). tCSRS tACQI tCSRH
How to Start a Conversion
Conversions are initiated with a write operation, which selects the mux channel and configures the MAX197 for either unipolar or bipolar input range. A write pulse (WR + CS) can either start an acquisition interval or initiate a combined acquisition plus conversion. The sampling interval occurs at the end of the acquisition interval. The ACQMOD bit in the input control byte offers two options for acquiring the signal: internal or external. The conversion period lasts for 12 clock cycles in either internal or external clock or acquisition mode.
tCS
CS
tCSWS
WR
tWR tDS
tCSWH tDH
CONTROL BYTE
tCONV
D7-D0
ACQMOD ="0" INT
tINT1
RD
HBEN
tD0
HGH-Z DOUT
tD01
HIGH / LOW BYTE VALID HIGH / LOW BYTE VALID
tTR
HGH-Z
Figure 5. Conversion Timing Using Internal Acquisition Mode 10 ______________________________________________________________________________________
Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface MAX197
tCS
CS
tCSRS
tCSRH
tCSWS
WR
tWR tDS
tACQI tCSHW tDH
tCONV
D7-D0
CONTROL BYTE ACQMOD = "1"
CONTROL BYTE ACQMOD = "0"
tINT1
INT
RD
HBEN
tD0
DOUT
tD01
HIGH / LOW BYTE VALID HIGH / LOW BYTE VALID
tTR
Figure 6. Conversion Timing Using External Acquisition Mode
How to Read a Conversion
A standard interrupt signal, INT, is provided to allow the device to flag the P when the conversion has ended and a valid result is available. INT goes low when conversion is complete and the output data is ready (Figures 5 and 6). It returns high on the first read cycle or if a new control byte is written.
shows a linear relationship between the internal clock period and the value of the external capacitor used.
Clock Modes
The MAX197 operates with either an internal or an external clock. Control bits (D6, D7) select either internal or external clock mode. Once the desired clock mode is selected, changing these bits to program power-down will not affect the clock mode. In each mode, internal or external acquisition can be used. At power-up, external clock mode is selected. Internal Clock Mode Select internal clock mode to free the P from the burden of running the SAR conversion clock. To select this mode, write the control byte with D7 = 0 and D6 = 1. A 100pF capacitor between the CLK pin and ground sets this frequency to 1.56MHz nominal. Figure 7
INTERNAL CLOCK PERIOD (ns)
2000
1500
1000
500
0 0 50 100 150 200 250 300 350
CLOCK PIN CAPACITANCE (pF)
Figure 7. Internal Clock Period vs. Clock Pin Capacitance 11
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Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface MAX197
External Clock Mode Select external clock mode by writing the control byte with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR timing relationships in internal and external acquisition modes, with an external clock. A 100kHz to 2.0MHz external clock with 45% to 55% duty cycle is required for proper operation. Operating at clock frequencies lower than 100kHz will cause a voltage droop across the hold capacitor, and subsequently degrade performance.
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
tCWS
WR ACQMOD = "0" WR GOES HIGH WHEN CLK IS HIGH
tCWH
CLK
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
WR ACQMOD = "0" WR GOES HIGH WHEN CLK IS LOW
Figure 8a. External Clock and WR Timing (Internal Acquisition Mode)
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
tDH
WR ACQMOD = "1" WR GOES HIGH WHEN CLK IS HIGH ACQUISITION STARTS CLK ACQUISITION ENDS
tCWS
ACQMOD = "0"
CONVERSION STARTS
tDH
WR ACQMOD = "1" WR GOES HIGH WHEN CLK IS LOW
tCWH
ACQMOD = "0"
Figure 8b. External Clock and WR Timing (External Acquisition Mode) 12 ______________________________________________________________________________________
Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface
__________Applications Information
Power-On Reset
At power-up, the internal power-supply circuitry sets INT high and puts the device in normal operation/external clock mode. This state is selected to keep the internal clock from loading the external clock driver when the part is used in external clock mode. external reference at REF must be able to deliver 400A DC load currents, and must have an output impedance of 10 or less. If the reference has higher input impedance or is noisy, bypass it close to the REF pin with a 4.7F capacitor to AGND. With an external reference voltage of less than 4.096V at the REF pin or less than 2.5V at the REFADJ pin, the increase in the ratio of the RMS noise to the LSB value (FS / 4096) results in performance degradation (loss of effective bits).
MAX197
Internal or External Reference
The MAX197 can operate with either an internal or an external reference. An external reference can be connected to either the REF pin or to the REFADJ pin (Figure 9). To use the REF input directly, disable the internal buffer by tying REFADJ to VDD. Using the REFADJ input eliminates the need to buffer the reference externally. When the reference is applied at REFADJ, bypass REFADJ with a 0.01F capacitor to AGND. The REFADJ internal buffer gain is trimmed to 1.6384 to provide 4.096V at the REF pin from a 2.5V reference. Internal Reference The internally trimmed 2.50V reference is gained through the REFADJ buffer to provide 4.096V at REF. Bypass the REF pin with a 4.7F capacitor to AGND and the REFADJ pin with a 0.01F capacitor to AGND. The internal reference voltage is adjustable to 1.5% (65 LSBs) with the reference-adjust circuit of Figure 1. External Reference At REF and REFADJ, the input impedance is a minimum of 10k for DC currents. During conversions, an
REF
26
4.096V CREF 4.7F
MAX197
AV = 1.638 REFADJ 25
VDD
10k
2.5V
Figure 9b. External Reference, Reference at REF
REF
26 CREF 4.7F
REF
26 CREF 4.7F
MAX197
MAX197
AV = 1.638 REFADJ 25 0.01F 10k
AV = 1.638 REFADJ 25 2.5V 0.01F
10k
2.5V
2.5V
Figure 9a. Internal Reference
Figure 9c. External Reference, Reference at REFADJ
______________________________________________________________________________________
13
Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface MAX197
Power-Down Mode
To save power, you can put the converter into lowcurrent shutdown mode between conversions. Two programmable power-down modes are available, in addition to a hardware shutdown. Select STBYPD or FULLPD by programming PD0 and PD1 in the input control byte. When software power-down is asserted, it becomes effective only after the end of conversion. In all power-down modes, the interface remains active and conversion results may be read. Input overvoltage protection is active in all power-down modes. The device returns to normal operation on the first WR falling edge during write operation. For hardware-controlled (FULLPD) power-down, pull the SHDN pin low. When hardware shutdown is asserted, it becomes effective immediately and the conversion is aborted. Choosing Power-Down Modes The bandgap reference and reference buffer remain active in STBYPD mode, maintaining the voltage on the 4.7F capacitor at the REF pin. This is a "DC" state that does not degrade after power-down of any duration. Therefore, you can use any sampling rate with this mode, without regard to start-up delays. However, in FULLPD mode, only the bandgap reference is active. Connect a 33F capacitor between REF and AGND to maintain the reference voltage between conversion and to reduce transients when the buffer is enabled and disabled. Throughput rates down to 1ksps can be achieved without allotting extra acquisition time for reference recovery prior to conversion. This allows conversion to begin immediately after power-down ends. If the discharge of the REF capacitor during FULLPD exceeds the desired limits for accuracy (less than a fraction of an LSB), run a STBYPD power-down cycle prior to starting conversions. Take into account that the reference buffer recharges the bypass capacitor at an 80mV/ms slew rate and add 50s for settling time. Throughput rates of 10ksps offer typical supply currents of 470A, using the recommended 33F capacitor value. Auto-Shutdown Selecting STBYPD on every conversion automatically shuts the MAX197 down after each conversion without requiring any start-up time on the next conversion.
OUTPUT CODE OUTPUT CODE 11... 111 11... 110 11... 101 000... 001 000... 000 111... 111 FULL-SCALE TRANSITION FS 1 LSB = 4096 1 LSB = 011... 111 011... 110
2FS 4096
00... 011 00... 010 00... 001 00... 000 0 1 2 3 INPUT VOLTAGE (LSB) FS - 3/2 LSB FS
100... 010 100... 001 100... 000 -FS 0V INPUT VOLTAGE (LSB) +FS - 1 LSB
Figure 10. Unipolar Transfer Function
Figure 11. Bipolar Transfer Function
14
______________________________________________________________________________________
Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface
Transfer Function
Output data coding for the MAX197 is binary in unipolar mode with 1LSB = (FS / 4096) and two's-complement binary in bipolar mode with 1LSB = ((2 x |FS|) / 4096). Code transitions occur halfway between successive-integer LSB values. Figures 10 and 11 show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. For full-scale (FS) values, see Table 1.
_Ordering Information (continued)
PART MAX197AENI MAX197BENI MAX197AEWI MAX197BEWI MAX197AEAI MAX197BEAI MAX197AMYI MAX197BMYI TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C PIN-PACKAGE 28 Narrow Plastic DIP 28 Narrow Plastic DIP 28 Wide SO 28 Wide SO 28 SSOP 28 SSOP 28 Narrow Ceramic SB** 28 Narrow Ceramic SB**
MAX197
Layout, Grounding, and Bypassing
Careful printed circuit board layout is essential for best system performance. For best performance, use a ground plane. To reduce crosstalk and noise injection, keep analog and digital signals separate. Digital ground lines can run between digital signal lines to minimize interference. Connect analog grounds and DGND in a star configuration to AGND. For noise-free operation, ensure the ground return from AGND to the supply ground is low impedance and as short as possible. Connect the logic grounds directly to the supply ground. Bypass VDD with 0.1F and 4.7F capacitors to AGND to minimize high- and low-frequency fluctuations. If the supply is excessively noisy, connect a 5 resistor between the supply and V DD , as shown in Figure 12.
** Contact factory for availability and processing to MIL-STD-883.
___________________Chip Topography
WR CLK V DD CS DGND RD REFADJ HBEN SHDN D7 CH7 0.231" (5.870mm) CH6 INT V CC REF
SUPPLY
CH5
+5V GND
D6 D5 D4 D3 CH4 CH3 CH2 D1 D2 D0 AGND 0.144" (3.659mm) CH0 CH1
4.7F R* = 5 0.1F ** VDD AGND DGND +5V DGND
MAX197
DIGITAL CIRCUITRY
TRANSISTOR COUNT: 2956 SUBSTRATE CONNECTED TO GND
* OPTIONAL ** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE
Figure 12. Power-Supply Grounding Connection
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15
Multi-Range (10V, 5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface MAX197
_________________________________________________________Functional Diagram
REF REFADJ 10k
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 SIGNAL CONDITIONING BLOCK AND OVERVOLTAGE TOLERANT MUX T/H CHARGE REDISTRIBUTION 12-BIT DAC 12
AV = 1.638
+2.5V REFERENCE
COMP
SUCCESSIVEAPPROXIMATION REGISTER CLK CLOCK 4 CS WR RD SHDN 8 INT CONTROL LOGIC AND LATCHES 4 MUX 8 THREE-STATE, BIDIRECTIONAL I/O INTERFACE D0-D7 8-BIT DATA BUS 8 8
HBEN
MAX197
VDD AGND DGND
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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